This document is intended to provide engineering insight regarding 25 GbE PHY configurations as noted by the IEEE standard and to address any observed interoperability issues related to the use and deployment of 25 GbE media in enterprise ecosystems based on customer use cases. This application note focuses specifically on the 25 GbE PHY link modes associated with our Intel® Ethernet Network Interface Card (NIC), System on Chip (SoC), and LAN on Motherboard (LOM) Portfolios, as well as the common media used for 25 Gb Ethernet applications; 25 GbE Twinaxial passive Direct Attach Copper (DAC) cables, 25 GbE optical transceivers, and 25 GbE backplane.
Understanding 25 GbE interoperability requires familiarity with the concept of a PHY link mode as it is defined in the 25 GbE IEEE standard and the 25 GbE/50 GbE Consortium Specification. PHY link modes are sometimes referred to as the PHY mode or link mode in some 25 Gb Ethernet arenas.
The IEEE 802.3-2018 standard defines categories for PHY link modes that did not exist in prior Ethernet generations. It also mandates certain sets of capabilities required by each link partner to guarantee correct operation with various 25 GbE media. The focus on the updated clauses is mainly on the different Forward Error Correction (FEC) modes required, and whether Auto-Negotiation (Clause 73) is required for the type of media used in 25 GbE applications.
Most 25 GbE switches and link partners in the ecosystem are defined by the degree to which they comply with these standards and specifications. Some support IEEE 802.3 only, while others only adhere to the Consortium specifications. For example, the support of 25 GbE Auto-Negotiation and the various FEC modes among existing switches is mixed and highly dependent on when the switch was manufactured. Some of the 25 GbE switches entered the ecosystem before the IEEE standard added these clauses, and as such, they do not support some of these features.