How do I Improve Memory Handling with 1st, 2nd, or 3rd Generation Intel® Xeon® Scalable Processors?

Higher rates of correctable and uncorrectable DRAM errors may be seen with the 1st Generation, 2nd Generation, or H SKUs of the 3rd Generation Intel® Xeon® Scalable Processors compared to previous generations.

As part of the Intel Platform Update (IPU) 2020.2 and newer, Intel issued processor microcode updates (MCU) and BIOS enhancements to system manufacturers that improve management of memory faults by enabling additional RAS (Reliability, Availability, Serviceability) features of the affected Intel® Xeon® Scalable Processors. Update your systems with the latest available BIOS release, including IPU 2020.2 (or newer), and then ensure enhanced Memory RAS features are enabled in the BIOS Setup screen. 

Contact the manufacturer of your server system or motherboard to check on the availability of a BIOS that includes IPU 2020.2 (or newer).

If you have an Intel® Server System or Intel® Server Board, follow these steps to obtain the latest BIOS and Firmware Update:

1. Go to the support website for your specific Intel® server product from Single Node Servers, Multi Node Servers, or Server Boards.
2. Select Driver & Software.
3. Set the filter to OS Independent.
4. Download the BIOS and Firmware Update in one of two formats: Package for UEFI or Intel® One Boot Flash Update.

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The affected Intel® Xeon® Scalable Processors implemented changes in Single Device Data Correction (SDDC). SDDC is a fundamental Intel RAS (Reliability, Availability, Serviceability) feature available on all platforms. As a result of these architectural changes and memory DIMM errors, there is a difference in which errors will be corrected between these processors and the previous generation of processors.