Intel Platform Update (IPU) 2021.1 and later versions include a microcode update that will impact the behavior of the Intel® Transactional Synchronization Extensions (Intel® TSX) and Performance Monitoring Unit (PMU) on the following processors:
|Family-Model||Stepping||Processor Families / Processor Number Series|
|06_55H||<=5||1st Generation Intel® Xeon® Scalable Processor Family and Intel® Xeon® Processor D Family based on Skylake microarchitecture|
|06_4EH, 06_5EH||All||6th Generation Intel® Core™ Processors and Intel® Xeon® Processor E3-1500m v5 product family and E3-1200 v5 product family based on Skylake microarchitecture|
|06_8EH||<=0xB||7th/8th Generation Intel® Core™ Processors and Intel® Pentium® Processors based on Kaby Lake/Coffee Lake/Whiskey Lake microarchitecture|
|06_9EH||<=0xC||8th/9th Generation Intel® Core™ Processors and Intel® Pentium® Processors based on Coffee Lake microarchitecture|
Intel TSX is a technology to enable hardware transactional memory. The PMU measures performance events using performance counters. For more details on Intel TSX, refer to the Web Resources About Intel® Transactional Synchronization Extensions. For more details on the PMU, refer to the Performance Monitoring section in Intel Software Developer’s Manual (Intel® SDM) Volume 3.
When the IPU 2021.1 microcode update is applied, the following changes will occur on the affected processors:
- Intel TSX will be disabled by default.
- The processor will force abort all Restricted Transactional Memory (RTM) transactions by default.
- A new CPUID bit CPUID.07H.0H.EDX(RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. Information about the CPUID instruction is in the Processor Identification and Feature Determination section in the Intel SDM.
- On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX and CPUID.07H.0H.EBX) continue to be set by default after microcode update.
- Workloads that were benefited from Intel TSX might experience a change in performance.
- System software may use a new bit in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled.
The Performance Monitoring Impact of Intel® Transactional Synchronization Extensions Memory Ordering Issue White Paper (PDF) provides details about the Intel TSX and PMU behavior changes due to the updated microcode in IPU 2021.1 and is a guide for PMU driver developers and performance tool developers. Intel does not expect this microcode update to affect users who do not use the PMU, or who only use updated PMU drivers and tools. Some advanced users of performance monitoring (Perfmon) may need to change their collection scripts and methodologies.
Note: PDF files require Adobe Acrobat Reader*