Intel Platform Update (IPU) 2021.2 and later versions include a microcode update that will impact the behavior of the Intel® Transactional Synchronization Extensions (Intel® TSX) and Performance Monitoring Unit (PMU) on the following processors:
Table 1: Processors Affected by IPU 2021.1 Changes to Intel TSX and PMU
Family-Model | Stepping | Processor Families / Processor Number Series |
06_4EH, 06_5EH | All | 6th Generation Intel® Core™ Processors and Intel® Xeon® Processor E3-1500m v5 product family and E3-1200 v5 product family based on Skylake microarchitecture |
06_8EH | <=0xB | 7th/8th Generation Intel® Core™ Processors and Intel® Pentium® Processors based on Kaby Lake/Coffee Lake/Whiskey Lake microarchitecture |
06_9EH | <=0xC | 8th/9th Generation Intel® Core™ Processors and Intel® Pentium® Processors based on Coffee Lake microarchitecture |
Intel® TSX is a technology to enable hardware transactional memory. The PMU measures performance events using performance counters. For more details on Intel® TSX, refer to the Web Resources About Intel® Transactional Synchronization Extensions. For more details on the PMU, refer to the Performance Monitoring section in Intel® Software Developer’s Manual (Intel® SDM) Volume 3.
When the IPU 2021.1 and later microcode update is applied, the following changes will occur on the affected processors:
Additionally, Intel TSX will be disabled by default in two additional CPUIDs with IPU 2021.2.
Table 2: Processors Affected by IPU 2021.2 Changes to Intel TSX
Family-Model | Stepping | Processor Families / Processor Number Series |
06_8EH | 0xC | 8th/10th generation Intel® Core™ processors, Intel® Pentium™ processors, and Intel® Celeron® processors based on Whiskey Lake, Comet Lake, and Amber Lake microarchitectures |
06_9EH | 0xD | 9th generation Intel® Core™ processors and Intel® Xeon® E processors based on Coffee Lake H microarchitecture |
When the IPU 2021.2 microcode is loaded, the same changes which were applied to the processors in Table 1 will also apply to the processors listed in Table 2, with two differences:
The Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue (PDF) provides details about the Intel TSX and PMU behavior changes due to the updated microcode in IPU 2021.1 and later versions and is a guide for PMU driver developers and performance tool developers. Intel does not expect this microcode update to affect users who do not use the PMU, or who only use updated PMU drivers and tools. Some advanced users of performance monitoring (Perfmon) may need to change their collection scripts and methodologies. The Intel® Transactional Synchronization Extension (Intel® TSX) Disable Update for Selected Processor Technical Paper (PDF) provides details about the Intel TSX behavior changes due to the updated microcode in IPU 2021.2. These technical paper should also be reviewed by developers that use Intel® Software Guard Extensions (Intel® SGX).
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