The Intel Hardware Security Academic Award recognizes groundbreaking research that advances the security, trustworthiness, and resilience of modern computing systems. Selected from a highly competitive pool of submissions, the 2026 finalists represent significant contributions across trusted execution environments, memory security, side-channel defenses, processor verification, and DRAM reliability.
The winners of the 2026 Intel Hardware Security Academic Award will be announced at the Intel Academic Security Conference, an invitation-only event that brings together leading academic researchers and industry technologists to explore emerging security challenges and innovations shaping the future of computing.
Finalists were evaluated based on:
- Novelty and originality of the research contribution
- Technical quality and rigor
- Significance of the problem addressed and the proposed solution(s)
- Potential impact on industry, the broader security ecosystem, and future computing technologies
- Relevance to hardware security research and practice
2026 Finalists
BadRAM: Practical Memory Aliasing Attacks on Trusted Execution Environments
Authors: Jesse De Meulemeester, Luca Wilke, Thomas Eisenbarth, David Oswald, Ingrid Verbauwhede, and Jo Van Bulck
BadRAM demonstrates a new class of memory aliasing attacks that undermine trusted execution environments by exploiting unexpected interactions in physical memory mappings. The work reveals previously overlooked attack surfaces and highlights the need for stronger memory isolation guarantees in confidential computing platforms.
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
Authors: Oğuzhan Canpolat, A. Giray Yağlıkçı, Geraldo F. Oliveira, Ataberk Olgun, Nisa Bostancı, İsmail Emir Yüksel, Haocong Luo, Oğuz Ergin, and Onur Mutlu
Chronus provides a comprehensive analysis of modern in-DRAM RowHammer defenses and identifies key performance and security limitations in existing approaches e.g. DDR5 JEDEC PRAC. The authors introduce a new mitigation mechanism that significantly improves protection against DRAM read-disturbance attacks while maintaining near-zero performance overhead.
Segue & ColorGuard: Optimizing SFI Performance and Scalability on Modern Architectures
Authors: Shravan Narayan, Tal Garfinkel, Evan Johnson, Zachary Yedidia, Yingchen Wang, Andrew Brown, Anjo Vahldiek-Oberwagner, Michael LeMay, Wenyong Huang, Xin Wang, Mingqiu Sun, Dean Tullsen, and Deian Stefan
Segue and ColorGuard demonstrate how existing x86 processor features can be repurposed to make WebAssembly (WASM) sandboxing both faster and more scalable. The techniques significantly reduce isolation overhead while increasing sandbox density by up to 15×, advancing the deployment of secure multi-tenant cloud, edge, and browser workloads.
Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
Authors: Zilong Wang, Gideon Mohr, Klaus von Gleissenthall, Jan Reineke, and Marco Guarnieri
This work introduces LeaSyn, an automated framework for synthesizing sound and precise leakage contracts directly from RTL implementation of open-source RISC-V processors. By automatically generating sound and precise security specifications that accurately characterize microarchitectural leakage, the approach helps bridge the gap between processor design and formal side-channel verification.
TLBlur: Compiler-Assisted Automated Hardening against Controlled Channels on Off-the-Shelf Intel SGX Platforms
Authors: Daan Vanoverloop, Andrés Sánchez, Flavio Toffalini, Frank Piessens, Mathias Payer, and Jo Van Bulck
TLBlur introduces an automated defense against controlled-channel attacks on Intel SGX systems by combining compiler instrumentation with hardware-assisted protection mechanisms. The solution reduces page-access leakage while remaining deployable on existing SGX platforms.