The Intel Hardware Security Academic Award recognizes groundbreaking research that advances the security, trustworthiness, and resilience of modern computing systems. Selected from a highly competitive pool of submissions, the 2026 finalists represent significant contributions across trusted execution environments, memory security, side-channel defenses, processor verification, and DRAM reliability.
The winners of the 2026 Intel Hardware Security Academic Award were announced Sept 30, on stage at the Intel Academic Security Conference, an invitation-only event that brings together leading academic researchers and industry technologists to explore emerging security challenges and innovations shaping the future of computing.
Finalists were evaluated based on:
- Novelty and originality of the research contribution
- Technical quality and rigor
- Significance of the problem addressed and the proposed solution(s)
- Potential impact on industry, the broader security ecosystem, and future computing technologies
- Relevance to hardware security research and practice
The 2026 IHSAA selection committee identified five finalist papers from a highly competitive field. From these finalists, one paper received the Recent Publication Award and two papers received Honorable Mention recognition.
Test of Time Award
Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu
https://users.ece.cmu.edu/~yoonguk/papers/kim-isca14.pdf
The Test of Time Award recognizes the groundbreaking work that first exposed DRAM disturbance errors, commonly known as Rowhammer. This research fundamentally changed the industry's understanding of memory reliability and security, inspired a decade of subsequent research, and continues to influence the design of secure and reliable computing systems today.
Recent Publication Award
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
Oğuzhan Canpolat, A. Giray Yağlıkçı, Geraldo F. Oliveira, Ataberk Olgun, Nisa Bostancı, İsmail Emir Yüksel, Haocong Luo, Oğuz Ergin, and Onur Mutlu
https://arxiv.org/abs/2502.12650
The Recent Publication Award recognizes Chronus for providing important insights into next-generation DDR5 Rowhammer mitigations while advancing the state of memory-system security and performance. The work analyzes emerging industry approaches and introduces a new mitigation mechanism that improves security while reducing system overhead. The authors have also open-sourced the implementation to enable future research and innovation.
Watch the Award Winner Panel Discussion with award recipients discussing the motivation, challenges, and future directions of memory-security research. https://youtu.be/rso5mvNYFFI
Honorable Mention
Segue & ColorGuard: Optimizing SFI Performance and Scalability on Modern Architectures
Shravan Narayan, Tal Garfinkel, Evan Johnson, Zachary Yedidia, Yingchen Wang, Andrew Brown, Anjo Vahldiek-Oberwagner, Michael LeMay, Wenyong Huang, Xin Wang, Mingqiu Sun, Dean Tullsen, and Deian Stefan
https://cseweb.ucsd.edu/~tullsen/asplos_segue.pdf
Segue and ColorGuard demonstrate how existing x86 processor features can be repurposed to make WebAssembly sandboxing both faster and more scalable. By significantly reducing isolation overhead while increasing sandbox density, the work advances the practical deployment of secure multi-tenant cloud, edge, and browser workloads.
Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
Zilong Wang, Gideon Mohr, Klaus von Gleissenthall, Jan Reineke, and Marco Guarnieri
This work introduces LeaSyn, an automated framework for synthesizing sound and precise leakage contracts directly from RTL implementations of open-source RISC-V processors. By automatically generating security specifications that accurately characterize microarchitectural leakage, the approach helps bridge the gap between processor design and formal side-channel verification, advancing hardware security assurance and verification.
2026 Finalists
BadRAM: Practical Memory Aliasing Attacks on Trusted Execution Environments
Authors: Jesse De Meulemeester, Luca Wilke, Thomas Eisenbarth, David Oswald, Ingrid Verbauwhede, and Jo Van Bulck
BadRAM demonstrates a new class of memory aliasing attacks that undermine trusted execution environments by exploiting unexpected interactions in physical memory mappings. The work reveals previously overlooked attack surfaces and highlights the need for stronger memory isolation guarantees in confidential computing platforms.
TLBlur: Compiler-Assisted Automated Hardening against Controlled Channels on Off-the-Shelf Intel SGX Platforms
Authors: Daan Vanoverloop, Andrés Sánchez, Flavio Toffalini, Frank Piessens, Mathias Payer, and Jo Van Bulck
TLBlur introduces an automated defense against controlled-channel attacks on Intel SGX systems by combining compiler instrumentation with hardware-assisted protection mechanisms. The solution reduces page-access leakage while remaining deployable on existing SGX platforms.