Intel Labs Presents Research on New Power Efficiency Techniques at 2021 Symposia on VLSI Technology and Circuits


  • The 2021 Symposia on VLSI Technology and Circuits, a two-track conference including the VLSI Circuit Symposium and the VLSI Technology Symposium, run from June 13-19, 2021

  • Intel researchers will present their latest research on breakthroughs in power efficiencies enabled by new materials and circuits in silicon at the VLSI Circuits Symposium


Intel will join leaders in the semiconductor industry during this year’s 2021 Symposia on VLSI Technology and Circuits, held online from June 13-19, to discuss the latest advancements and new directions in very large-scale integration (VLSI) circuit and system implementations. The VLSI Symposia has been running for more than 30 years and is sponsored by the IEEE Electron Devices Society and Solid-State Circuits Society, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics and Communication Engineers.

This year’s theme for the conference is “VLSI Systems for Lifestyle Transformation,” and Intel will present research on silicon photonics for breakthrough IO power/performance in next generation products. In addition, Intel will present details of its first gallium nitride (GaN) voltage regulator featuring heterogenous integration of new materials with silicon circuits. Intel will also showcase the latest research advances in platform and system on a chip (SoC) power delivery and management.

James Jaussi, senior principal engineer, director of the PHY Research Laboratory, Intel Labs

Following is an overview of the four Intel Labs papers presented during the 2021 Symposium on VLSI Circuits Advance Program.  

*Please note: These papers will not be accessible via Intel’s website and are only accessible to conference attendees. Please visit the VLSI website and register for the conference to access these papers.

In addition, J. Blackwell, synthetic chemist at Intel Corp., will discuss “Mechanism and Materials for Advanced Patterning” during a workshop on “Materials Introductions – A Path Forward for All Devices,” on June 13th. Both D. Nikonov and A. Khosrowshahi of Intel Corp., will present, “Hardware for Next Generation AI,” during a short course on “Enabling a Future of Even More Powerful Computing,” on June 14th. R. Krishnamurthy of Intel Corp. will present “Challenges and Opportunities for Sub-7nm In-Memory/Near-Memory Computing, AI Accelerators, and Hardware Security” during the “Technologies for Post COVID-19 Era” forum on June 19th.

2021 VLSI Symposium on VLSI Circuits Program Papers


  • Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS

Jahnavi Sharma, Hao Li, Zhe Xuan, Ranjeet Kumar, Chun-Ming Hsu, Meer Sakib, Peicheng Liao, Haisheng Rong, James Jaussi, and Ganesh Balamurugan Intel Corporation, USA

A 4λ×112 Gb/s/λ hybrid-integrated silicon photonic TX suitable for 400G Ethernet modules and co-packaged optics is presented. The photonic IC (PIC) uses cascaded micro-ring modulators (MRMs) with integrated heaters for efficient wavelength division multiplexing (WDM). The 28nm CMOS electronic IC includes PAM4 MRM drivers with nonlinear FFE and control circuits to stabilize MRM performance against process and temperature variations. A thermal control scheme based on sensing MRM photocurrents is used to minimize monitoring hardware in the PIC. Measured results demonstrate 112 Gb/s PAM4 operation with <0.7 dB TDECQ from each of the 4 channels. To our best knowledge, this is the highest per-λ data rate reported for an O-band ring-based WDM transmitter.


  • A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors

Nachiket Desai, Harish K. Krishnamurthy, William Lambert, Jingshu Yu, Han Wui Then, Nicolas Butzen, Sheldon Weng, Christopher Schaef, N. Nidhi, Johann Rode, Justin Sandford, Kaladhar Radhakrishnan, Krishnan Ravichandran, Bernhard Sell, James W. Tschanz, and Vivek De, Intel Labs, Components Research, Technology Development Group, Hillsboro, Oregon, USA

A 5V-input buck converter using a low-voltage GaN power transistor with 5-10x improved FoM over Si has been employed to build a high-frequency (3-10 MHz), high-density (9A/mm2) buck converter. The converter employs on-die gate clamps and is co-packaged with a CMOS Companion Die on a 4mm x 4mm package, achieving 94.2% peak efficiency at 5Vin/1Vout at 3MHz switching frequency with a 40nH inductor.


  • A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers

Suhwan Kim, Harish Krishnamurthy, Sally Amin, Sheldon Weng, Jin Feng, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James Tschanz, Vivek De, Intel Corporation, Hillsboro, Oregon, USA 

A 1S direct-battery-attach buck converter with a 5-stack, thin-gate-FinFET power train delivers a peak efficiency of 89.2% for 3.8Vn/1.8Vout, with 10x higher power density (~15A/mm2), switching at up to 10x higher frequency (40MHz) using 4x-10x lower inductance (10-100nH) than current state-of-the-art technologies. Cascaded self-timed drivers and soft-switching low-side drivers minimize complexity in driving ten individual power switches safely.


  • A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction

Zakir K. Ahmed, Nachiket Desai, Harish K. Krishnamurthy, Sheldon Weng, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz and Vivek De, Intel Labs, Hillsboro, Oregon, USA

A dual-input, digital hybrid buck-LDO system featuring a 300MHz Fully Integrated Voltage Regulator (FIVR) and a Computational Transient Management Controller (CTMC)-based Low Dropout (LDO) regulator is presented. The high-speed, parallel CTMC-LDO reduces the FIVR input resonance (82% peak-to-peak voltage-swing reduction). The CTMC-LDO operates without any communication with the FIVR and can act as a clamp (54% droop & 69% settling time reduction) or share current (0-100%) in parallel with the FIVR, thus increasing load capacity.


  • All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP

C. Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, F. Merchant, J. Tschanz, M. Khellah, Intel Corporation, Austin, Texas, USA and Circuit Research Lab, Intel, Hillsboro, USA

A 10nm 4-core x86 IP with multiple low-power states including C1 (clock-gated core), C6 (power-gated core) and a new state called C1LP where the core voltage is lowered to its retention voltage (VRETENTION) is presented. This all-digital closed-loop unified retention clamp for C1LP and wake up for C6 shows power savings of 33% and 28% respectively, for core/IP, with 120ns wake up latency while addressing impact of PVT variations.