Device Family: Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF


Last Modified: January 30, 2018
Version Found: v17.1
Bug ID: FB: 531536;
IP: Stratix 10 External Memory Interfaces, Arria 10 External Memory Interfaces

How is the address map ordering of the Avalon bus to the DDR4 memory defined for the Intel® Stratix® 10 External Memory Interfaces IP ?

Description

The DDR4 address map ordering is defined by the parameter in the DDR4 IP controller tab -> Efficiency -> Address Ordering
There are 3 supported ordering combinations of the following parameters:

  • CID (chip ID in a stacked interface)
  • CS (chip select in a mutiple rank interface)
  • Row
  • Column
  • Bank
  • BG (bank group)

Workaround/Fix

For multiple rank interfaces, CS is one bit wide for dual rank and two bits wide for quad rank. For a single rank interface, there is no CS bit.
For interfaces using 3D stack or through-silicon-via, CID is one bit wide for a 2-high stack and two bits wide for a 4-high stack. For a non-stacked interface, there is no CID bit.
Row, column, bank address widths and bank group width are defined in the DDR4 data sheet.

The sum of the widths of the CID, CS, BG, Row, Column and Bank address parameters is 3 bits larger than the Avalon address port width.
The lower 3 bits of the column address are set to 0 in the controller because the Avalon bus width is eight times wider than the external memory data bus in a quarter-rate interface. Therefore the lower 3 bits for column addressing are removed when mapped to the Avalon address.

An example of the DDR4 IP address mapping using memory components with a single chip select and address width parameters is shown below:

Row 16, Column 10, Bank 2, Bank Group 2.  Address Ordering is CS-CID-Row-Bank-Col-BG.
The Avalon bus address width is 27 bits shown as amm_address[26..0] in the IP Block Symbol view or in the RTL top level file port description.
The mapping is :

Row[15..0]               = amm_address[26:11]
Bank[1..0]                = amm_address[10:9]
Col[9..3]                   = amm_address[8:2]
Bank Group[1..0]    = amm_address[1:0]


This address mapping flow is applicable for all supported configurations of Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 External Memory Interfaces IP for DDR4, DDR3, DDR3L and LPDDR3.

This information is scheduled to be added in a future version of the Intel Stratix 10, Intel Arria 10 and Intel Cylone 10 External Memory Interface IP User Guides.