Article ID: 000086356 Content Type: Troubleshooting Last Reviewed: 08/18/2023

Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel® Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel® Quartus® Prime Software versions?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces (EMIF) IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel® Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel® Quartus® Prime Pro Edition Software versions?

     

    Mixing the phase 1 and phase 2 bitstreams that are generated from different Intel® Quartus® Prime Pro Edition Software versions is a non-supported use case.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4. 

    Related Products

    This article applies to 1 products

    Intel® Stratix®