The Shared Memory Partion design example configures the memory protection rules in the hard processor system (HPS) SDRAM controller. The design example includes a companion System Console toolkit that allows the user to exercise the HPS SDRAM Controller and test the established rules.

The design is provided for the following Intel^® FPGA development Kit:

Cyclone^® V SoC Development Kit

The design leverages the ability for users to send Avalon® Memory Mapped commands over JTAG. The Avalon-MM commands are routed to a JTAG to Avalon Master Bridge, which is tied to the FPGA To HPS AXI* Bridge on the HPS. From there the data is directed into the L3 Interconnect where it is routed based on the destination address. A command with the appropriate destination address is routed to the SDRAM Controller Subsystem where it will ultimately be executed.

Hardware Design Specifications

Cyclone V HPS
1GB of DDR3-SDRAM

Figure 2. Design Example Memory Partitions

Memory Partition Breakdown:

The 1GB of memory is partitioned using two rules. The first rule sets the access region for the MPU. The MPU is granted access from 0MB to 512MB. The second rule sets the access region for the L3 Interconnect. The L3 Interconnect has access from 319MB to 1,024MB. The overlap of these two rules results in a "Shared" region which both the MPU and L3 interconnect can access.

Using This Design Example

Download the Cyclone V Memory Partition design example (.zip file)

Download the Cyclone V Memory Partition design example readme (.txt file)

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.

The .zip file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for re-building the design.

A visual breakdown of the System Console toolkit commands are included below. Additional instructions are included in the readme.txt file.

System Console Read/Write:

To read data from a particular address through the L3 Interconnect to the HPS SDRAM Controller simply enter the address you wish to read from and click the "Read" (grey)
To write data to a particular address through the L3 Interconnect to the HPS SDRAM Controller enter the address you wish to write to and the byte of data you wish to write and click the "Write data" button (blue)

System Console HPS Read:

To read data from a particular address via the MPU enter a '1' at address location 0x1ffffff4 using the "Write data" Button illustrated in blue
Enter the destination address in the bottom right data cell circled in grey
Click the "Write address" button to have the MPU read the contents of the entered address

System Console HPS Write:

To write data to a particular address via the MPU enter a '2' at address location 0x1ffffff4 using the "Write data" Button illustrated in blue
Enter the destination address in the bottom right data cell circled in grey
Click the "Write address" button
Change the address in the middle address cell to 0x1fffffd4 circled in blue
Enter the byte of data you wish to write in the adjacent data cell circled in blue
Click the "Write data" button to have the MPU perform the write operation

Related Links

Cyclone V SoC Handbook (PDF)
GSRD User Manual

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.