The Shared Memory Partion design example configures the memory protection rules in the hard processor system (HPS) SDRAM controller. The design example includes a companion System Console toolkit that allows the user to exercise the HPS SDRAM Controller and test the established rules.
The design is provided for the following Intel® FPGA development Kit:
Hardware Design Specifications
- Cyclone V HPS
- 1GB of DDR3-SDRAM