VHDL Template for Inferring DSP Blocks in Stratix III and IV FPGAs

Altera's Stratix® III and Stratix IV FPGA families have dedicated high-performance digital signal processing (DSP) blocks optimized for DSP applications. This template shows examples of how to infer DSP blocks with different features from VHDL code in Stratix III and Stratix IV devices.

Each of the following DSP operations (with resource utilized in the examples) fits into one DSP block 18-bit element: .

  • Four multiplier adder
  • Four multiplier accumulator
  • Four multiplier adder with shift registered input
  • Complex multiplication
  • Eight multiplier adder with output adder chain

In addition, when register packing occurs for any of these DSP operations, no extra logic cells are required for the registers.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera® Hardware Reference Design License Agreement.

Files in the zip download include:

  • four_mult_add - folder contains the Quartus® II development software project and source file for the four multiplier adder example
  • four_mult_accum - folder contains the Quartus II project and source file for the four multiplier accumulator example
  • four_mult_add_shift_register_input - folder contains the Quartus II project and source file for the four multiplier adder with shift registered input example
  • complex_mult - folder contains the Quartus II project and source file for the Complex multiplication example
  • sum_of_eight_adder_chain - folder contains the Quartus II project and source file for the eight multiplier adder with output adder chain example

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