Verilog HDL: Gray Counter

This example describes an 8-bit Gray-code counter design in Verilog HDL. The Gray code outputs differ in only one bit for every two successive values.

Figure 1. Gray Counter Top-Level Diagram

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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

 

 

Table 1. Gray Counter Port Listing

Port NameTypeDescription
clkInputClock input
enableInputEnable input
resetInputReset input
gray_count[7:0]Output8-bit data output

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