Verilog HDL: Adder/Subtractor

This example describes a two-input, 8-bit adder/subtractor design in Verilog HDL. The design unit dynamically switches between add and subtract operations with an add_sub input port.

Figure 1. Adder/Subtractor Top-Level Diagram

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Table 1. Adder/Subtractor Port Listing

Port NameTypeDescription
dataa[7:0], datab[7:0]Input8-bit data inputs

Input port to enable dynamic switching between add and subtract operations

clkInputClock input
result[8:0]Output8-bit data output and a carry/borrow MSB bit

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