Evolutions in technology are improving beyond traditional programmable digital signal processing (DSP) device capabilities. The degree of flexibility offered by programmable logic and the associated throughput benefits make FPGAs and PLDs increasingly attractive alternatives for performance-hungry applications.
In modern multi-channel systems, where similar data arrives at very high sampling rates and is subject to simultaneous algorithmic transformations, FPGA implementations with high I/O rates and parallel structures provide a tangible benefit at a fraction of the cost of a multi-processor-based DSP approach.
Altera’s set of DSP documentation presents the design flow commonly used in the FPGA design community.
DSP Builder for Intel FPGAs Handbook
- Volume 1: Introduction to DSP Builder for Intel FPGAs
- Volume 2: DSP Builder Standard Blockset
- Volume 3: DSP Builder for Intel FPGAs Advanced Blockset
DSP IP Core
- BCH IP Core User Guide
- CIC IP Core User Guide
- FFT MegaCore Function User Guide
- FIR Compiler II IP Core User Guide
- High-speed Reed-Solomon IP Core User Guide
- LDPC IP Core User Guide
- NCO IP Core User Guide
- Reed-Solomon II IP Core User Guide
- Turbo IP Core User Guide
- Viterbi IP Core User Guide
Device Selection and Architecture
- DSP Blocks in Stratix IV Devices
- Variable Precision DSP Blocks in Stratix V Devices
- DSP Blocks in Arria GX Devices
- DSP Blocks in Arria II Devices
- Embedded Multipliers in Cyclone IV Devices
DSP Applications Using FPGAs
- FPGAs for High-Performance DSP Applications
- Soft Multipliers For DSP Applications
- AN 306: Implementing Multipliers in FPGA Devices
- Versatile Digital QAM Modulator
- Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors
- Implementation of CORDIC-Based QRD-RLS Algorithm on Altera Stratix FPGA with Embedded Nios Soft Processor Technology
Reference Designs
- AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices
- AN 245: Filtering Reference Design Lab
- AN 317: Turbo Encoder Co-processor Reference Design
- AN 371: Automotive Graphics System Reference Design
- AN 421: Accelerating WiMAX DUC & DDC System Designs
- AN 439: Constellation Mapper and Demapper for WiMAX
- AN 442: Tool Flow for Design of Digital IF for Wireless Systems
- AN 450: Uplink Desubchannelization for WiMAX
- AN 451: Downlink Subchannelization for WiMAX
- AN 475: Crest Factor Reduction for OFDMA Systems
- AN 506: QR Matrix Decomposition
- AN 515: 24K FFT for 3GPP LTE RACH Detection
- AN 544: Digital IF Modem Design with the DSP Builder for Intel FPGAs Advanced Blockset
Release Notes