altdq Intel® FPGA IP

Data strobe Intel® FPGA IP. The altdq Intel® FPGA IP transmits and receives data on both edges of the reference clock. The altdq Intel® FPGA IP is available for Cyclone® IV.

Intel recommends instantiating this function with the IP Catalog.

  • For this Intel® FPGA IP, the IP Catalog generates output files with multiple entities or modules. The top-level entity or module is located at the bottom of the file.
  • If your design does not connect to a DQS bus, you should use the altddio_in, altddio_out, oraltddio_bidir Intel® FPGA IP rather than the altdq Intel® FPGA IP.
  • To interface with the p and n-pins, you can instantiate your altdq Intel® FPGA IP then instantiate an I/O buffer Intel® FPGA IP.
  • When you create your Intel® FPGA IP, you can use the IP Catalog to generate a netlist for third-party synthesis tools.
Note: More information is available on the altdq Intel® FPGA IP on the Altera website.