VHDL Component Declaration

The following VHDL component declaration is located in the VHDL Design File (.vhd) Definition ALTERA_MF_COMPONENTS.vhd located in the <Quartus^® Prime installation directory>\libraries\vhdl\altera_mf directory.

component altclklock

        generic (

                clock0_boost    :       natural := 1;

                clock0_divide   :       natural := 1;

                clock0_settings :       string := "UNUSED";

                clock0_time_delay       :       natural := 0;

                clock1_boost    :       natural := 1;

                clock1_divide   :       natural := 1;

                clock1_settings :       string := "UNUSED";

                clock1_time_delay       :       natural := 0;

                clock2_boost    :       natural := 1;

                clock2_divide   :       natural := 1;

                clock2_settings :       string := "UNUSED";

                clock2_time_delay       :       natural := 0;

                clock_ext_boost :       natural := 1;

                clock_ext_divide        :       natural := 1;

                clock_ext_settings      :       string := "UNUSED";

                clock_ext_time_delay    :       natural := 0;

                inclock_period  :       natural := 10000;

                inclock_settings        :       string := "UNUSED";

                intended_device_family  :       string := "UNUSED";

                invalid_lock_cycles     :       natural := 5;

                invalid_lock_multiplier :       natural := 5;

                lpm_hint        :       string := "UNUSED";

                lpm_type        :       string := "altclklock";

                operation_mode  :       string := "UNUSED";

                outclock_phase_shift    :       natural := 0;

                valid_lock_cycles       :       natural := 5;

                valid_lock_multiplier   :       natural := 5 );

        port(

                clock0  :       out std_logic;

                clock1  :       out std_logic;

                clock2  :       out std_logic;

                clock_ext       :       out std_logic;

                fbin    :       in std_logic := '1';

                inclock :       in std_logic;

                inclocken       :       in std_logic := '1';

                locked  :       out std_logic

        );

end component;