altclklock IP Core

ParameterizedPhase-Locked Loop (PLL) Definition IP core. The altclklock IP core enables PLL circuitry. The phase-locked loop synthesizes a clock signal that is based on a reference clock. The altclklock IP core can reduce clock delay and skew, and can be used to generate internal clocks that operate at frequencies that are multiples of the frequency of the system clock.

The altclklock Intel® FPGA IP can also improve setup and hold times.

Note: This IP core is only support in Quartus Prime Standard Edition.