Design Simulation
Simulation allows you to verify design behavior before device programming.Quartus® Prime software supports RTL- and gate-level design simulation in various third-party simulators.
Simulating a design involves:
- Setting up your simulator working environment
- Compiling simulation model libraries
- Running the simulator
- Interpreting the results
Quartus® Prime software supports both Verilog
HDL and VHDL simulation of encrypted and unencrypted Altera FPGA IP cores.
Note: If your design includes Altera FPGA IP cores, you must compile any
corresponding IP simulation models in your simulator with the rest of your design and
testbench. Quartus® Prime software generates and copies the
simulation models for IP cores to your project directory.
Note: For more information about using
EDA simulators, refer to the Quartus® Prime Pro Edition User
Guide: Third-party Simulation.