M9K memory block Definition

A synchronous, true dual-port memory block, with registered inputs and optionally registered outputs, available in supported device (Cyclone® IV and Stratix® IV) family devices. The M9K block is useful for storing processor code, implementing lookup schemes, and implementing large memory applications. Each block is a 256 x 36 RAM block and contains 9,216 programmable bits, including parity bits. You can configure the M9K block as true dual-port, dual-port, and single-port RAM, and ROM. You can use a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) to preload the memory contents when the M9K memory block is configured as a RAM, ROM, or MLAB. All RAM instances are kept in the form of block RAM until after analysis and synthesis, when the Fitter converts block RAM to MLABs to balance out the resource usage, or if the design specifies MLAB.

Each M9K memory block supports two clock-enable controls, which allows each input register and core memory cell to use either clock-enable controls or no gating clock control. The output register supports one clock-enable control or no gating clock control.

The Write Enable (WE) and Read Enable (RE) controls are independent in M9K memory blocks. Independent WE and RE controls allow you to reduce power consumption under circumstances when data output during a write operation is not critical.

The following table lists the configurable sizes for the M9K memory block:

Operation Mode

M9K Memory Block Size

Single-port and ROM

8192 x 1 4096 x 1 2000 x 4 1024 x 9 512 x 18 256 x 36


Write x M / Read x N W x Y / R x Z

M, N= 1, 2, 4, 8, 16, or 32 Y, Z= 9, 18, or 36

True dual-port

port A x M / port B x N A x Y / B x Z

M, N = 1, 2, 4, 8, or 16 Y, Z = 9 or 18