M10K memory block Definition

A synchronous, true dual-port memory block, with registered inputs and optionally registered outputs, available inArria® V and Cyclone® V family devices. You can use the M10K block for storing processor code, implementing lookup schemes, and implementing large memory applications. You can configure the M10K block as true dual-port, simple dual-port, and single-port RAM and ROM. You can use a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) to preload the memory contents when the M10K memory block is configured as a RAM orROM. All RAM instances are kept in the form of RAM slices until after Analysis and Synthesis, when the Fitter assigns RAM slices to M10K RAM blocks or MLABs to balance out the resource usage, or if the design specifies MLAB.

Each M10K memory block supports three clock-enable controls, which allow each input register and core memory cell to use either clock-enable controls or no gating clock control. The output register supports one clock-enable control or no gating clock control. Clock muxing is balanced, which prevents skew between clock paths.

The Write Enable (WE) and Read Enable (RE) controls are independent in M10K memory blocks. Independent WE and RE controls allow you to reduce power consumption when data output during a write operation is not critical. Byte Enable (BE) signals allow for more fine-grained write control. There is no error correction code (ECC) status feature for M10K.

The following table lists the configurable sizes for the M10K memory block:

Operation Mode

M10K Memory Block Sizes

Single-port and ROM

1K x 8 1K x 10 2K x 4 2K x 5 4K x 2 8K x 1 256x 32 256x 40 512 x 16 512x 20


Write x M / Read x N or W x xY / Read xZ

M, N= 1, 2, 4, 8, 16, 32 and Y, Z= 5, 10, 20, 40

True dual-port

Port A xM / port B xN or Port A xY / port B xZ

M, N = 1, 2, 4, 8, 16 and Y, Z = 5, 10, 20