ID:13591 SystemVerilog warning at <location>: index undefined for "<name>"

CAUSE: In an assignment or expression at the specified location in a SystemVerilog Design File (.sv), you used an index that falls outside the declared range of the current array dimension. An invalid index in an assignment will be ignored. An invalid index in an expression will return the default initial value for the array's element type, which may be don't care.

ACTION: To avoid this warning, use an index value that falls within the bounds of the array dimension.