SystemVerilog Design File (.sv) Definition

An ASCII text file (with the extension .sv) created with the Intel® Quartus® Prime Text Editor or any other standard text editor. A SystemVerilog Design File describes design logic in the SystemVerilog language, which is an extension to Verilog.

A SystemVerilog Design File can contain any combination of the SystemVerilog constructs supported by the Intel® Quartus® Prime software. For more information, see "Intel® Quartus® Prime Support for SystemVerilog 2005."