ID:13598 SystemVerilog error at <location>: const-qualified variable "<name>" is not legal in constant expressions

CAUSE: In a constant expression at the specified location in a SystemVerilog Design File (.sv), you referred to a variable that was declared as const. SystemVerilog does not allow const variables in constant expressions, even if they are declared with a constant expression for a value. Const variables outside functions and tasks are not initialized until after elaboration but before simulation begins, so they cannot be used during elaboration itself.

ACTION: Replace the const variable with a parameter, constant literal, genvar, or any other legal constant expression.