SGR-30022: Clock Port and Any Other Port of a Register Driven by the Same Signal Source

This rule is a sub-rule of ../jsa1564419200808.htm#jsa1564419200808. It reports a violation only when your design contains clock signal sources that connect to ports other than the clock ports of the same register.


A clock signal source should drive only input clock ports of registers. Clock port and any other port of a register should not be driven by the same signal source.




Analysis and Elaboration

Device Family

  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX