altera_soft_core_jtag_io Intel^® FPGA IP

Soft core JTAG I/O Intel^® FPGA IP. This Intel^® FPGA IP provides a standard JTAG interface that controls all JTAG accessible extensions. It controls the SLD JTAG hub to which SLD debug nodes connect. Optionally, it provides a signal to select whether the JTAG accessible extension is controlled by the JTAG I/O on this Intel^® FPGA IP or by the JTAG I/O on the device.

A minimal JTAG controller in the Intel^® FPGA IP allows tools to communicate to all JTAG accessible extension instances connected to sld_hub. The JTAG IR instructions implemented are BYPASS,IDCODE, USR0, and USR1. All other IR values are mapped to BYPASS. This JTAG controller returns the IDCODE value of 0x020030DD, which is assigned to be the soft JTAG controller. The tdo output is not tri-stated.

The altera_soft_core_jtag_io Intel^® FPGA IP is available for all Intel device families supported by the Intel^® Quartus^® Prime software. You can only use one instance of this Intel^® FPGA IP in a project.