# Fitter Resource Usage Summary Report

## All Device Families Except Arria^{®} V , Cyclone^{®} V , Stratix^{®} V, and Intel^{®} Arria^{®} 10

Summarizes Fitter usage statistics for resources in the selected device. Different resources are reported depending on the device family you select.

The Resource column displays usage statistics for device resources including: logic elements, HCells and HCell Macros, DSP Blocks, registers, adaptive logic modules (Adaptive Logic Module (ALM) Definition), Combinational Adaptive Look-Up Table (ALUT) Definition, logic array blocks (Logic Array Block (LAB) Definition), I/O pins, virtual pins Definition, UFM Definition blocks, global clock Definition, signals, SERDES Definition transmitter and receiver channels, gigabit transceiver block (GXB) Definition transmitter and receiver channels phased-lock loops (Phase-Locked Loop (PLL) Definition), JTAG resources, memory blocks, Programmable Power Technology Tiles Definition, interconnect usage, and fan-out.

The Usage column displays resource usage as a fraction, where the amount of the resource used in your design is divided by the total quantity of the specific resource available on the targeted device.

## Arria^{®} V, Cyclone^{®} V , and
Stratix^{®} V Device Families

The
Fitter Resource Usage Smmary report forArria^{®} V , Cyclone^{®} V , and Stratix^{®} V device
families also contains the % column, which displays
the percent of a given resource used in your design.

The Fitter
Resource Usage Summary report forArria^{®} V , Cyclone^{®} V , and Stratix^{®} V device
families displays a detailed analysis of logic utilization based on calculations of ALM
usage.

Logic utilization is the metric for the number of ALMs necessary to implement your design, displayed as a fraction of the total ALMs available on the target device (ALMs needed / total ALMs on the device). The report displays logic utilization as the result of operations on the number of ALMs fulfilling different functions.

ALMs needed—lists the results of the following calculation:

ALMs used in final placement—Estimate of ALMs recoverable by dense packing + Estimate of ALMs unavailable

ALMs used in final placement—Calculated as the sum of the following factors:

- ALMs used for LUT logic and registers—Lists the number of ALMs that implement both look-up table (LUT) logic functions and registers. ALMs are fracturable, that is, the Fitter configures the ALM for a variety of uses; for example, a 1-input LUT driving a FF, two 6-input LUTs in shared-LUT mode driving two registers.
- ALMs used for LUT logic—Lists the number of ALMs that implement only LUT logic.
- ALMs used for registers—Lists the number of ALMs that are used by passing a signal through to the register without invoking a logical operation.
- ALMs used for memory (up to 1/2 of total ALMs)—Lists the number of ALMs used to implement memory bits in core logic. These ALMs operate in LUTRAM mode, and are grouped together in Memory LABs (MLAB Definition).

- Estimate of ALMs recoverable by dense
packing—An estimate the number of ALMs that can be recovered as the design
grows. This metric estimates the amount of recoverable logic in units of ALMs. During
Place & Route optimization, the Intel
^{®}Quartus^{®}Prime software permits logic to use more area than is required, improving optimization metrics such as Fmax. However, as the design grows and more logic is added, you may need to know what amount of that space can be recovered. For example, the Intel^{®}Quartus^{®}Prime software may be able to recover ALMs by packing unrelated LUTs and registers together into the same ALMmore aggressively, but this aggressive packing my reduce the Fmax performance of your design.

- Estimate of ALMs unavailable—An
estimate of ALMsthe number of ALMs in LABs that are not used, and are unlikely to be
usable, due to various design and device constraints. ALMs combine to form LABs and each
LAB contains ten ALMs. After your design undergoes Place & Route, some LABs typically
contain unused ALMs, however, not all unused ALMs can be targeted. Specific reasons for
unusable ALMs include constrained logic, signal conflicts, LAB input limits and virtual
I/Os. The Estimate of ALMs unavailable metric is
the sum of the following factors:
- Due to location constrained logic—The number of ALMs where you are allowed to use only part of the ALM. If you specify the location of a logic element in the top or bottom part of the ALM, no other unlocked logic elements are combined with that element in the top or bottom part of the ALM.
- Due to LAB-wide signal
conflicts—The number of control signals, such as
`clock`,`sload`, and`sclr`, that drive elements in each LAB are restricted. If the populated ALMs in a LAB use most of the control signals, it is unlikely that other logic can be added to the LAB. - Due to LAB input limits—The number of signals that can arrive into each LAB is restricted. If the populated ALMs in a LAB use most of the LAB inputs, it is unlikely that other logic could be added to the LAB.
- Due to virtual I/Os—When you
specify virtual I/Os, the Intel
^{®}Quartus^{®}Prime software implements them as LUTs, then packs and places them to allocate the space they potentially occupy. However, they do not count as used, nor can they be packed with non-virtual core logic.

Difficulty packing design—This estimate is based on the types of packing algorithms required in order to fit your design using the number of LABs on the targeted device. The clustering phase of fitting attempts increasingly more aggressive packing strategies, until all logic can be fit or a no-fit due to clustering is declared. The packing algorithms consists of four categories; Low, Medium, High, and No-Fit. High packing difficulty may indicate that fitting the design into the target device required Fmax performance trade-offs.

Total LABs: partially or completely used—The number of LABs that contain ALMs implementing the design. LABs can be fully used, with all ALMs implementing logic, or partially used, with as little as a single ALM implementing logic. This metric distinguishes between Logic LABs and Memory LABs, which can be up to Â½ of the total LABs.

Combinational ALUT usage for logic—Core user logic in a design is synthesized into Combinational Adaptive Look-Up Table (ALUT) Definition, of one to seven inputs. Combinational ALUT usage is a count of the total number of such functions in the design, and is a purely logical count. The exact amount of ALM hardware required to implement the logic is unknown prior to fitting. A rough estimate of the amount of ALM hardware needed for implementing LUT functions can be computed by assuming that all six-input functions will use a full ALM (though it may not be the case for the particular design in question), and that all smaller input functions will be successfully packed in pairs into an ALM (although a small percentage of such functions may not be successfully paired, and each use its own ALM). For example, in a design with 20,000 Combinational ALUT functions of up to 5-inputs and 10,000 Combinational ALUT functions of 6 and 7-input functions, the total combinational ALUT count is 30,000, but the number of ALMs used to implement the design can range from 15,000 to 30,000. Note that these are theoretical limits. You must run the fitter to obtain an accurate utilization in terms of ALMs.

Combinational ALUT usage for route-throughs—Lists LUT resources used for the purpose of driving a signal into a register that is not driven directly by a LUT packed in the same ALM.

In an ALM, the Fitter can choose from multiple paths to drive a register's data input signal. There are dedicated paths, sometimes referred to as a "sneak paths", that bypass the LUT logic; and there are direct paths, sometimes referred to as"route throughs", that drive through the LUT logic. In certain situations, it may be faster to drive the register via a route through if the LUT is otherwise unused for other logic. If the Fitter uses a route through, overall logic utilization is not reduced because the LUT was unavailable to pack a real logic function.

This metric is not part of the logical count of Combinational ALUTs in the design, since it is an implementation detail.

Dedicated logic registers—Displays the total number of logic registers in the design, to be implemented with core logic (ALMs). The exact amount of ALM hardware required to implement the register logic is unknown prior to fitting. The Dedicated logic registers metric displays the usage of registers By type and By function.

By type—Displays the number of Primary logic registers and Secondary logic registers as fractions; logic registers used/total logic registers.

By function—Displays the number of logic registers used as implementation registers and routing optimization registers.

Note: Arria^{®}V , Cyclone^{®}V , Stratix^{®}V, and Intel^{®}Arria^{®}10 device family ALMs contain four registers; the two registers from the previous architecture are reported in the Primary logic registers row, and two additional registers are reported in the Secondary logic registers row. Both primary and secondary registers can be used in the same way as registers in previous architectures.