To perform a timing simulation with command-line commands
To perform a timing simulation of a Verilog HDL or VHDL design with the Mentor Graphics® ModelSim® (OEM) software with command-line commands:
Note: Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the ModelSim® - Intel® FPGA Edition or ModelSim® PE or SE main window into a text
file and name the file with a .do extension (that is,<file name>.do). Use this script to recompile the libraries if you update them.
To run a macro script:
- From the Mentor Graphics® ModelSim® main window, choose Execute Macro.
- In the Execute Do File dialog box, locate your ModelSim® macro file (.do).
- Click Open.