To perform a timing simulation with command-line commands

To perform a timing simulation of a Verilog HDL or VHDL design with the Mentor Graphics® ModelSim® (OEM) software with command-line commands:

Note: Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the ModelSim® - Intel® FPGA Edition or ModelSim® PE or SE main window into a text file and name the file with a .do extension (that is,<file name>.do). Use this script to recompile the libraries if you update them.

To run a macro script:

  1. From the Mentor Graphics® ModelSim® main window, choose Execute Macro.
  2. In the Execute Do File dialog box, locate your ModelSim® macro file (.do).
  3. Click Open.
  1. If you have not already done so, compile libraries and design files with the ModelSim® software.
  2. If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the .vo or .svo or set up the signals in the .vho.
  3. To load the design with minimum, typical, or maximum timing values, type the following commands at the ModelSim® prompt:
    vsim -t ps -sdf(min | typ | max) +transport_int_delays +transport_path_delays /= <design name> .sdo work. <top-level design entity>

    To direct the ModelSim® software to generate a .vcd that you can then use to perform power analysis in the Intel® Quartus® Prime Power Analyzer, type the following command at the ModelSim® prompt:

    source<testbench or design instance name>_dump_all_vcd_nodes.tcl

    The Tcl Script File (.tcl) Definition directs the ModelSim® software to monitor and write the output signals contained in the .tcl to a .vcd during simulation.