- To compile the Verilog Output
File (Verilog Output File (.vo) Definition), VHDL
Output File (VHDL Output File (.vho) Definition), or
SystemVerilog Output File (SystemVerilog Output File (.svo)) and testbench files
(if you are using a testbench) into the working
directory:
- On the Compile menu, click
Compile.
- In the Library list of the
Compile HDL
Source Files dialog box, select the work
library.
- In the Files of Type list,
select All Files
(*.*), and in the Look in list, select
the name of the .vo, .svo, or .vho.
- Click Compile.
- Repeat steps 1b to 1d for the
testbench file (if you are using one) that
instantiates the .vo, .svo, or .vho.
- Click Done.
- If your design contains
device-wide reset or device power up signals, and
if you have not already done so, set up the
signals in the Verilog Output File or set up the
signals in the VHDL Output File.
- On
the Simulate menu, click Start
Simulation. The Start Simulation
dialog box appears.
- If you are simulating a
Verilog HDL design, click the Verilog tab. Under
Pulse
Options, type
0
in the Error Limit and Rejection Limit
boxes.
- If you are simulating a VHDL
design, to specify the Standard Delay Format Output File (.sdo) Definition
- Click the SDF tab.
- Click Add.
- In the Add SDF Entry dialog
box, click Browse. The Select SDF File dialog
box appears.
- In the Files of type list,
select All Files
(*.*).
- Select the .sdo.
- Click Open.
- Click OK.
Note: If you are using a testbench file
to provide simulation stimuli to your design, in
the Apply to
region box, specify the path to the
design instance in the testbench, starting from
the top-level design file.
- If you are simulating a
Verilog HDL design, to specify the ModelSim
precompiled libraries:
- Click the Libraries tab.
- In the Search Libraries (-L)
box, click Add.
- Expand the Select library list to
see the list of all libraries, including
precompiled ModelSim-Intel FPGA Edition libraries,
and select the appropriate precompiled
ModelSim-Intel FPGA Edition libraries.
- Click OK.
- Click the Design tab.
- In the Name list, click the
+ icon to
expand the work directory and select the design
entity that corresponds to the .sdo.
- Click Add.
- Select the top-level design
file or testbench.
- Click Add.
- If you are simulating
high-speed circuits (including designs that use
HSSI, LVDS, or PLLs):
- Click the Other tab.
- In the Other options box
type
+transport_int_delays
and +transport_path_delays
.
- Click OK.
- Click Load.
- To direct the ModelSim-Intel
FPGA Edition software to generate a Value Change Dump File (.vcd) Definition that you can
then use to perform power analysis in the
Quartus® Prime
PowerPlay®
Power Analyzer, type the following command at the
ModelSim prompt:
source <testbench or design instance
name>_dump_all_vcd_nodes.tcl
- The Tcl Script File directs
the ModelSim-Intel FPGA Edition software to
monitor and write the output signals contained in
the Tcl Script File to a Value Change Dump File
during simulation.
- Perform the timing
simulation in the ModelSim-Intel FPGA Edition
software.
Note: The EDA
Netlist Writer generates a functional simulation
netlist rather than a timing simulation netlist
for designs that specify
Stratix® V or newer device families, even if
you specified a timing simulation
netlist.