maxfan Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify. You can use this option to reduce the load of critical signals in the design, thereby improving performance.

To use the maxfan synthesis attribute, you can specify the maxfan synthesis attribute in a comment that is on the same line as the register for which you want Analysis & Synthesis to control fan-out. In the comment, precede the synthesis attribute with the synthesis keyword and place an equal sign (=) between the synthesis attribute and the maximum value.

For example, in the following code, the comment /* synthesis maxfan = 200 */ directs Analysis & Synthesis to duplicate the clkgen register to ensure that the register's fan-out does not exceed the maximum value of 200:

reg clk_gen /* synthesis maxfan = 200 */;