Verilog HDL Synthesis Attributes and Directives

The Quartus® Prime software supports the following Verilog HDL synthesis attributes and synthesis directives, which you can use in a Verilog Design File (.v) Definition or SystemVerilog Design File (.sv) Definition to direct Analysis & Synthesis to perform or not perform certain actions when synthesizing a design:

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Attribute or Directive

Description

altera_attribute

A Verilog HDL synthesis attribute that specifies the value of Quartus® Prime options and assignments for Verilog HDL objects (modules, instances, nets, and registers).

chip_pin

A Verilog HDL synthesis attribute that assigns device pins to a port on a module.

direct_enable

A Verilog HDL synthesis attribute that guides Quartus® Prime Integrated Synthesis as to which signals it should prefer as clock enable signals to the registers.

full_case

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to treat unspecified state values in a Verilog Design File Case Statement as don't care values, and therefore to treat the Case Statement as "full".

keep

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular net when optimizing combinational logic.

maxfan

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify.

max_depth

A Verilog HDL synthesis attribute that specifies the maximum depth of the TriMatrix memory blocks used to implement an inferred RAM or ROM.

multstyle

A Verilog HDL synthesis attribute that specifies the type of implementation style for multiplication operations (*) in your HDL source.

noprune

A Verilog HDL synthesis attribute that prevents the Quartus® Prime software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.

parallel_case

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File Case Statement.

preserve

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.

ram_init_file

A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory.

ramstyle

A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM.

romstyle

A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred ROM.

read_comments_as_HDL

A Verilog HDL synthesis directive that directs Analysis & Synthesis to perform logic synthesis on portions of the design code that are in comments.

syn_encoding

A Verilog HDL synthesis attribute that determines how the Quartus® Prime software should encode the states of an inferred state machine.

translate_off translate_on

Verilog HDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.

useioff

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement input, output, and output enable registers in I/O cells that have fast, direct connections to an I/O pin, when possible.

verilog_input_version

A Verilog HDL synthesis directive that specifies the Verilog HDL language version to use

To use a synthesis attribute or directive in a Verilog Design File you can use the (* and *) delimiters. For example, you can use the following code to use the preserve synthesis attribute:


(* preserve *) reg my_reg;

You can also use a synthesis attribute or directive if you specify the synthesis attribute or directive in a comment in the file. The comment can use one of the following formats:


/* <comment> */
// <comment>

In the comment, precede the synthesis attribute or directive with the synthesis keyword. You can also precede the synthesis attribute or directive with one of the following keywords:

  • Synopsys®
  • pragma
  • exemplar

For example, you can use the following comment to use the preserve synthesis attribute in a Verilog Design File:


reg my_reg /* synthesis preserve */;

To use more than one synthesis attribute and/or directive for a single node, separate the synthesis attributes and/or directives with a space. For example, you can use the following comment to use the maxfan and preserve synthesis attributes for a single node:


reg my_reg /* synthesis maxfan = 16 preserve */;

Synthesis attributes and directives are also known as "pragmas". Synthesis directives are also known as "logic synthesis directives." Verilog HDL synthesis attributes and directives are case-sensitive.