altera_attribute VHDL Synthesis Attribute
A VHDL synthesis attribute for making assignments in the
Quartus® Prime software to objects
in your HDL source files. You can use it to embed assignments in your source files
when
the assignments do not have a specific VHDL synthesis attributes. The attribute takes
a
single string value with the same syntax as an assignment in a Tcl script or the Quartus Prime Settings File (.qsf) Definition. The
Quartus® Prime software only
supports altera_attribute
on entities, instances, ports, and registers.
If applied to any other object, the synthesis attribute is ignored.
altera_attribute
, unless assignments made with the
altera_attribute
are more specific. More specific assignments
override less specific assignments. For example, an entity assignment overrides a
global
assignment, and an instance assignment overrides an entity assignment.
Assignments
made with the altera_attribute
synthesis attribute are not displayed
in the Assignment Editor or written to the
Quartus® Prime Settings
File. Assignments made with the altera_attribute
synthesis attribute
are listed in the Source Assignments report in the Analysis
& Synthesis folder of the Compilation Report.
To use the altera_attribute
synthesis attribute in a VHDL Design File (.vhd) Definition, declare the synthesis attribute
using an Attribute Declaration, and then associate the altera_attribute
synthesis attribute with a VHDL object using an Attribute Specification. The value
of
the altera_attribute
attribute you associate with the object must be a
single string argument containing a list of QSF assignments separated by semicolons
(;
), as shown in the following code:
attribute altera_attribute : string;
attribute altera_attribute of <object> : <entity class> is "<assignment>[;<assignment>..]"
-name <name_1> <value_1> [-to <target_1>] [-from <source_1>] [-section_id section_1];
-name <name_2> <value_2> [-to <target_2>] [-from <source_2>] [-section_id section_2];
[...];"
In this code:
- <name_1> and <name_2> are the names of QSF variables.
- <value_1> and <value_2> are the QSF variables' corresponding values.
- <target_1> and <target_2> are optional tags which specify the target instances this assignment should apply to within this entity.
- <source_1> and <source_2> are optional tags which specify the source instances that this assignment should apply to within this entity. <section_1> and <section_2> are optional tags which specify the sections that this assignment should apply to.
Not all assignment types would need a target, a source or a section. If a QSF variable requires a string value, use nested quotes around the value, as shown in the following example, which uses a non-existent variable and value:
attribute altera_attribute of reg1: signal is "-name VARIABLE_NAME
""STRING_VALUE"""
The following example shows how to use the altera_attribute
synthesis
attribute to set the power-up level of an inferred register.
signal my_reg : std_logic attribute altera_attribute : string; attribute altera_attribute of my_reg : signal is "-name POWER_UP_LEVEL HIGH"; process(clk) begin if(rising_edge(clk)) then my_reg <= d; end if; end process;
The following example shows how to use the altera_attribute
synthesis
attribute to specify a synthesis logic option for an entity. In this example, the
synthesis attribute turns off the Auto Shift Register Recognition
logic option. You can associate the attribute with an entity or an architecture for
the
entity. This example shows an altera_attribute
associated with an
architecture.
entity my_entity is -- Declare ports and generics end my_entity; architecture rtl of my_entity is attribute altera_attribute : string; attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF"; begin -- Specify the architecture body end rtl;
The following example shows how you can also use altera_attribute
for
more complex assignments involving more than one instance. In this example, the
following VHDL sample uses an altera_attribute
to cut all timing paths
from q1
to q
2
:
signal q1, q2 : std_logic; attribute altera_attribute : string; -- Equiv to
set_instance_assignment -name CUT ON -from q1 -to q2 attribute altera_attribute of
q1
: signal is "-name CUT ON -to q2";
You may specify either the -to
option or the -from
option in a single altera_attribute
; integrated synthesis automatically
sets the remaining option to the target of the altera_attribute
. You
may also specify wildcard characters Definition for either option. For
example, if you specify *
for the -to
option instead
of q2
, the
Quartus® Prime software cuts all timing paths from
q
1
to every other register in the design.