To perform a functional simulation with command-line commands

To use the Mentor Graphics ModelSim-Intel FPGA Edition software, provided with the Quartus^® Prime software, to perform a functional simulation of a VHDL or Verilog HDL design that contains Intel-specific components using command-line commands:

If you have not already done so, set up a ModelSim-Intel FPGA Edition project with command-line commands.
To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench), type the following commands at the ModelSim prompt.
For VHDL designs:
```
vcom -work work <design name> .vhd
vcom -work work <testbench> .vhd
```
For Verilog HDL designs:
```
vlog -work work <design name> .v
vlog -work work <testbench> .v
```
To load the design, type the following commands at the ModelSim prompt.
For VHDL designs: vsim work.
<top-level design entity>
For Verilog HDL designs:
vsim -L altera_mf_ver -L lpm_ver <top-level design module>
Perform the functional simulation in the ModelSim-Intel FPGA Edition software.
Note: Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the ModelSim-Intel FPGA Edition main window into a text file and name the file with a .do extension (that is,<file name>.do). Use this script to recompile the libraries if you update them.
To run a macro script:
1. From the Mentor Graphics ModelSim main window, click Execute Macro.
2. In the Execute Do File dialog box, locate your ModelSim macro file (.do).
3. Click Open.