- If you have not already done so, set up a project with the ModelSim-Intel FPGA Edition software.
- To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench):
- On the Compile menu, click Compile.
- In the Library list of the Compile Source Files dialog box, select the work library.
- In the File name list, type the directory path and file name of the .v file or .vhd file.
orIn the Files of Type list, select All Files (*.*), and in the Look in list select the .v file
or .vhd file.
- Click Compile.
- Repeat steps 2b to 2d to compile the testbench file(s).
- Click Done.
- To load the design:
- On the Simulate menu, click Simulate.
- If you are simulating a Verilog HDL design, to specify the ModelSim-Intel FPGA Edition precompiled libraries:
- Click the Libraries tab.
- In the Search Libraries (-L) box, click Add and select the appropriate libraries.
- Click OK.
- In the Name list, click the + icon to expand the work directory.
- Select the top-level design file to simulate.
- Click Add.
- Click Load.
- Perform the functional simulation in the ModelSim-Intel FPGA Edition software.
Important: If your design contains the alt2gxb IP Core, refer to the appropriate megafunction topic for required settings information.