Analysis & Synthesis generates reports to display the following resource information based on the settings selected in the Compiler Settings page. Similar information is generated by the Fitter.
Summarizes usage statistics for resources including logic elements in various configurations, HCells and HCell Macros, combinational cells for routing, DSP Blocks, multiplier block Definition, registers, adaptive logic modules (Adaptive Logic Module (ALM) Definition) logic array blocks (Logic Array Block (LAB) Definition), I/O pins, virtual pins Definition, and fan-out.
Reports the utilization of the following resources for each entity in the design logic cells, registers, memory bits, macrocells, DSP block elements, DSP block 9x9, 18x18, and 36x36 multipliers, virtual pins, pins, carry chain logic cells, logic cells that only utilize the look up table (LUT) in the logic cell, logic cells that only use the register, and logic cells that use both the register and the LUT. The specific resources listed in the Compilation Report might vary depending on the device selected.
The Compilation Report list can contain multiple Resource Utilization by Entity reports, one generated during Analysis & Synthesis, partition based reports, and one generated during fitting. The Analysis & Synthesis Resource Utilization by Entity report contains the resource usage of entities in the compilation hierarchy as calculated after logic synthesis, but before fitting. Because the Fitter's register packing Definition operation can reduce the number of logic cells in the design, the total usage reported in the Analysis & Synthesis Resource Utilization by Entity report may be greater than the total usage reported in the Fitter Resource Utilization by Entity report or the Fitter Resource Usage Summary report.
The Logic Cells, LUT-Only LCs, Register-Only LCs, LUT/Register LCs and Carry Chain LCs columns list the logic cells used by the design entity (including the top level design entity and all sub-entities) and the number of logic cells (in parentheses) used by the design entity at that level in the hierarchy.
The logic cell combinationals count may be inaccurate if the inputs or outputs of an entity are not registered. Having unregistered inputs and outputs can cause logic to be optimized across entity boundaries, which means that logic that was originally in one entity may be named after logic in an adjacent entity and may thus be accounted towards the wrong entity.
Reports the following information about RAM memory in the design after Analysis & Synthesis:
Reports the details on IP cores used in your design— including vendor, IP core name, version of the Quartus® Prime Standard Editionsoftware when this core is created, release date, entity instance, license type, and the name and location of the IP include file.
Reports the operating modes and the number used of each type of DSP block Definition used by the design in supported device families, including multipliers, adders, accumulators, and DSP block 9-bit elements. This report appears only if the design includes DSP blocks.