Fitter Netlist Optimizations Report

Reports the major changes applied by the Fitter to the design netlist. Major changes include register packing; duplicating a logic cell; retiming a register; deleting a logic cell; inverting a signal; or modifying a node in a more general way, such as moving an input from one logic cell to another.

The Fitter Netlist Optimizations Report only appears if the Fitter applies one of the optimizations. Following are examples of ways to control Fitter optimizations:

register packing Definition can merge logic cell registers into I/O cells, RAM blocks, and DSP blocks. In some cases it can also duplicate registers and invert signals. Register packing may also merge LUT-only logic cells with register-only logic cells, but the results of this merge does not appear in the report window.
Physical synthesis can duplicate registers, retime registers, and modify combinational logic in more general ways.
PLL merging merges together two or more compatible phase-locked loops (PLL) driven by the same clock source, reducing the total number of PLLs used in a design.
Manual Logic Duplication duplicates individual nodes.

The report displays the following information:

Heading	Description	Value
Node	Shows the affected node. To locate the node, right-click the report row, and then click Locate options on the shortcut.	`<node name>`
Action	Shows one of the actions taken by the Fitter.	Created \| Duplicated \| Modified \| Deleted \| Absorbed \| Inverted \| Packed Register \| Retimed Register \| Merged PLL
Operation	Shows which Fitter optimization algorithm applied the changes.	`<algorithm or operation name>`
Reason	Shows why the optimization was applied. There are three main categories for optimization: user assignment, timing or area optimizations, and changes required to ensure a valid fit.	Timing optimization \| Location assignment \| Fast Input Register assignment \| Fast Output Register assignment \| Fast Output Enable Register assignment \| Manual Logic Duplication \| Carry chain legalization \| SignalProbe register pipelining \| PLL Usage Optimization
Node Port	Shows the affected output port on the affected node. This column may remain empty.	`<port name>`
Node Port Name	Shows the name of the node port.	<node port name>
Destination Node	Shows whether the node is a duplicate node or a node that absorbs the subject node. This column may remain empty.	`<duplicate node name> \| <absorbing node name>`
Destination Port	Shows the affected port on the destination node for register packing and duplication. This column may remain empty, for example, many changes that Physical Synthesis performs generate no value.	`<port name>`
Destination Port Name	Shows the name of the destination port.	<destination port name>