| List of Messages | |
CAUSE: You assigned the CLKLOCKx1 Input Frequency logic option to one or more nodes in the current design. However, Analysis & Synthesis is ignoring this logic option because the current target device you specified for the design does not support ClockLock PLLs.
ACTION: No action is required. If you want to use a ClockLock PLL, target a device family that supports ClockLock PLLs.
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