List of Messages |
CAUSE: You turned on the Auto Packed Registers logic option and turned on the Fast Input Register logic option for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However, the Quartus Prime software cannot pack the nodes because doing so would require modification of an inverter node, but the inverter node may not be modified due to one or more design rules intended to preserve design functionality, correct timing analysis, or design partitioning. See the submessages for details.
ACTION: If the register node should be packed, then in many cases you can override the design rules by assigning the Always Allow value for the Netlist Optimizations logic option to the inverter node. If the register node should not be packed, turn off the Fast Input Register, Fast Output Register, or Fast Output Enable Register option on the register node or I/O cell or remove the PLL source synchronous mode assignment on the I/O cell.
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