List of Messages |
CAUSE: The specified global clock driver is fed by an input pin (or pair of differential input pins) that is not placed onto a dedicated REFCLK input pin location. To improve jitter performance and reduce clock skew, Altera recommends using dedicated REFCLK I/Os to drive global clocks
ACTION: To improve jitter performance and reduce clock skew between the I/O input and the global clock driver, modify your design or the placement constraints to use dedicated REFCLK pins to feed the clock input signal to the specified global clock driver.
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