ID:12121 Remapped PLL WYSIWYG primitive clk[<number>] output port "<name>" to sclkout[<number>] output port "<name>"

CAUSE: You changed the target device family for a design, and compiled the design. The design instantiated a PLL that feeds an LVDS receiver and/or LVDS transmitter WYSIWYG primitive for the old target device family. While remapping the PLL from the old target device family to the new target device family, the Quartus Prime software remapped the specified clk[] output port on the WYSIWYG primitive to the specified sclkout[] output port, including the clk[] output port's corresponding parameters (such as multiply_by, divide_by, and phase_shift).

ACTION: No action is required.