Parameterized, family-dependent primitives that correspond to device features, such as logic cells, I/O elements, product terms, and Embedded System Blocks (ESBs). WYSIWYG primitives are contained in Verilog Quartus Mapping Files (.vqm) and EDIF Input Files (.edf) generated by other EDA tools, as well as in Altera-generated library of parameterized modules (LPM) functions. If a VQM File, EDIF Input File, or LPM function contains WYSIWYG primitives, the Quartus® Prime Standard Edition Compiler creates atom representations from those WYSIWYG primitives as it synthesizes the design, so that the atoms preserve the WYSIWYG structure of the netlist file. The atoms generated by the Quartus® Prime Standard Edition software are similar to the WYSIWYG primitives in netlist files generated by other EDA tools. WYSIWYG primitive variations include WYSIWYG I/O, CAM, RAM, ClockLock PLL, gigabit transceiver block (GXB), PLL, LCELL, and MCELL primitives.
WYSIWYG primitives and their Quartus® Prime Standard Edition"“generated atom representations allow other EDA synthesis tools to achieve better implementation of a design. WYSIWYG primitives and atoms also give AMPP partners more control over how their designs are implemented in a device. Altera provides simulation models of atoms for functional and timing simulation in the \quartus\eda\sim_lib directory.