ID:12114 Created CLKCTRL WYSIWYG primitive "<name>" to remap PLL clock enable port used by clock output "<name>"

CAUSE: You changed the target device family for a design, and compiled the design. The design instantiated a PLL for the old target device family. While remapping the PLL from the old target device family to the new target device family, the Quartus Prime software created the specified CLKCTRL WYSIWYG primitive to remap the PLL clock enable port that the specified output uses.

ACTION: No action is required.