List of Messages |
CAUSE: The specified WYSIWYG Clock Delay Control primitive was intended for a different device family and was converted to a wire with minimum delay.
ACTION: If this conversion is acceptable, no action is required. If this conversion is not acceptable, and if you are using an EDA tool, contact the technical support for the EDA tool regarding this message. If the specified WYSIWYG was used to implement a double data rate memory interface, Altera strongly recommends the use of the ALTMEMPHY Megafunction to implement the interface.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.