| List of Messages | |
| User location constraints | You created location constraints with fixed locations. |
| User-defined LogicLock region | You assigned nodes and entities to a LogicLock region. An LE may have no constraints but have a constraint source listed as a LogicLock region. This happens if the Fitter removes the LogicLock due to conflicting user constraints. In this case a warning message is issued. |
| User global signal promotion | Nodes and entities are connected to a signal that you placed on a dedicated clock routing network. The driver of the signal may be locked to a specific location that can drive that network. |
| Auto Global signal promotion | Nodes and entities are connected to a signal that the Auto Global Clock logic option placed on a dedicated clock routing network. The driver of the signal may be locked to a specific location that can drive that network. |
| Regional clock | Nodes and entities are connected to a signal that is driven from a dedicated regional clock network. They are constrained to the area reachable by that network. |
| Fast regional clock | Nodes and entities are connected to a signal that is driven from a dedicated fast regional clock network. They are constrained to be in the area reachable by that network. |
| Register packing | Nodes and entities were combined with other nodes and entities by the Auto Packed Registers logic option, and the resulting node or entity is constrained to a location that satisfies all of the location constraints on the original node or entities. |
| I/O register packing (TDC) | Nodes and entities include a register which has been placed in an I/O register to improve circuit performance. The resulting I/O is constrained to a location that satisfies all of the location constraints on the original nodes and entities. |
| I/O register packing (Fast I/O) | Nodes and entities include a register which has been placed in an I/O register by the Fast Output Register or Fast Input Register option. The resulting I/O is constrained to a location that satisfies all of the location constraints on the original nodes and entities. |
| Merging RAM slices | Nodes and entities are embedded memory cells placed into a single RAM, and it is constrained to a location that satisfies all of the location constraints on the original embedded memory cells. |
| Constraint propagation through a DSP block | Nodes and entities are part of a DSP block. They are connected to other nodes and entities in that DSP block that have location constraints. The location constraints were copied, with suitable adjustments, to these nodes and entities. |
| Carry chain location propagation | Nodes and entities include part of a carry chain. Other nodes and entities in that carry chain have location constraints. The location constraints have been copied, with suitable adjustments, to these nodes and entities. |
| Register cascade chain location propagation | Nodes and entities include part of a register cascade chain. Other nodes and entities in that chain have location constraints. The location constraints have been copied, with suitable adjustments, to these nodes and entities. |
| CONFIG Blocks(RUBLOCK/CRCBLOCK) | A node or entity is a configuration block or a dedicated I/O connected to a configuration block. (RUBLOCK/CRCBLOCK) |
| PLL | A node or entity is a PLL or a dedicated I/O connected to a PLL. |
| LVDS | A node or entity is a dedicated differential I/O pin. |
| CDR | A node or entity is a GXB PLL or is connected to a GXB PLL. |
| LogicLock incremental compile preferred location constraints | You created preferred locations for nodes or entities in a LogicLock region. Preferred locations are used as a suggested initial placement for incremental placement and the Fitter may not enforce them. |
| Fitter netlist optimization incremental compile preferred location constraints | Nodes and entities were given preferred locations by Fitter netlist optimizations. Fitter netlist optimizations take advantage of placement information to optimize the netlist for fMAX. It creates preferred location assignments on nodes and entities so that the optimized netlist can be placed using incremental placement. |
| I/O standards pin placement | Nodes and entities include I/O cells that were placed while trying to obey restrictions on I/O banks. |
| Dedicated global/regional or fast regional clock input pins | Nodes and entities are global/regional or fast regional clock I/O pins. |
| Internal global | A node or entity drives a global signal that can only be driven from this location. |
| DQS pin placement | The node or entity is a DQS I/O or DQ I/O pin. |
| JTAG placement | The node or entity is used for JTAG boundary-scan testing. |
| DSP block output programmable invert constraint | Nodes and entities include an inverter implemented by a programmable inverter on the output of a DSP block. The resulting DSP block is constrained to a location that satisfies all of the location constraints on the original nodes and entities. |
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