List of Messages |
CAUSE: In a Module Instantiation port connection in the WYSIWYG primitive to more than one signal. You must connect a port with one bit to only one signal with one bit. This error may also have occurred if you created or edited a VQM File manually.
ACTION: Make sure the port with one bit in the WYSIWYG primitive connects only to a signal with one bit. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.
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