| List of Messages | |
CAUSE: The fan-in of the specified WYSIWYG ClockLock PLL primitive feeds more than two destinations (that is, more than two ClockLock PLL buffers). However, the fan-in of a WYSIWYG ClockLock PLL primitive can feed no more than two destinations.
ACTION: Correct the WYSIWYG ClockLock PLL primitive in the design so the fan-in feeds no more than two destinations.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.