List of Messages |
CAUSE: The Fitter cannot place a delay locked loop (DLL), Leveling Delay Chain, and DQS I/O group in such a way that connectivity requirements between these blocks can be satisfied. This message may appear because one or more of the associated blocks have been placed in locations can never connect to the other blocks by location or region constraints, for example, DLL constrained to different edge of FPGA than a related DQS I/O pin.
ACTION: For more information about which DLL, Leveling Delay Chain, and DQS I/O Group in your design that could not be placed, refer to the submessages. Check location constraints applied to these blocks and ensure that they correspond to valid locations on the FPGA that can be connected.
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