List of Messages |
CAUSE: You have set operation_mode to m18x18_systolic and used the second pipeline register (parameter second_pipeline_clock is not set to none) for the specified DSP block WYSIWYG primitive but the second pipeline clock and the input systolic clock source are different. Parameters second_pipeline_clock and input_systolic_clock should have the same value.
ACTION: Assign the same value for second_pipeline_clock and input_systolic_clock.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.