List of Messages |
CAUSE: You have used input registers on multiple dynamic control signals by specifying the values for load_const_clock, accumulate_clock, negate_clock, and sub_clock for DSP block WYSIWYG primitive but not all the values are the same. These clock signals need to be driven by the same clock source. However, the clock signals can be individually bypassed (meaning no input register is used for the corresponding dynamic control signal) by assigning the value none.
ACTION: Make sure all the specified signals share the same value or assign the value none.
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