List of Messages |
CAUSE: The specified DSP block WYSIWYG primitive has 2 clocks which drive 2 registers that cannot be used simultaneously.
ACTION: Change the clock parameter to NONE for either one of the register that should not be used in the current DSP preadder mode.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.