List of Messages |
CAUSE: The specified port of the specified WYSIWYG primitive has an illegal CLOCK_ENABLE parameter. The specified port must have the same CLOCK_ENABLE parameter as the other pipeline register nodes in the DSP block slice.
ACTION: Remove the pipeline register of the specified port of the specified WYSIWYG DSP block output, or make sure the pipeline register of the specified port uses the same CLOCK_ENABLE as the other pipeline register nodes in the DSP block slice.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.