List of Messages |
CAUSE: The specified DSP block WYSIWYG primitive was originally created for a different family and has an output width with the specified value in the specified mode, but the output width is greater than maximum value for the specified mode that is supported in the target family's DSP block. As a result, this WYSIWYG primitive cannot be remapped to the target family.
ACTION: Do not use DSP blocks with the specified mode with an output width greater than the indicated value. For example, do not use Verilog Quartus Mapping File (.vqm) files containing DSP blocks with specified mode and an output width greater than the indicated maximum value.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.