List of Messages |
CAUSE: The specified WYSIWYG RAM primitive uses the specified parameters, but the parameters have values that are inconsistent with each other. The parameters must have the same values when the ports for port A and port B use the same specified clock.
ACTION: If you are using an EDA tool, contact the technical support for the EDA tool regarding this message. Otherwise, modify the WYSIWYG RAM primitive so that the port A and port B ports have the same values.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.